1. Field of the Invention
The present invention relates to a metal-insulator-semiconductor field effect transistor (which will be referred to as a "MISFET") and, more particularly, to a MISFET which is suitable for raising the breakdown voltage of a sub-micron-channel-length MISFET and which is excellently free from any degradation even with hot carrier injection. On the other hand, the present invention relates to a complementary metal-oxide-semiconductor-field effect transistor (which will be referred to as a "CMOSFET") and, more particularly, to a submicron-channel-length CMOSFET of high breakdown voltage, which can operate with a power supply of 5 V even in a gate length equal to or less than 0.5 .mu.m.
2. Description of the Prior Art
In order to reduce the channel length of the MISFET, it is the present practice to make a gate insulator thin, a source-drain distance small, and a source-drain junction shallow. As a result of this tendency, the maximum problem of the MISFET at present is a drop of a source-drain breakdown voltage. The drop of the so-called "punch-through voltage", which is caused as a result that a depletion layer extending from the drain side reaches the source region can be obviated by increasing the substrate doping concentration. This in turn decreases the avalanche breakdown voltage. Especially, the avalanche breakdown voltage (which will be referred to as "BVDS") for the zero bias of the gate, the source and the substrate drops far more than a breakdown voltage of intrinsic p-n junction because increase in the surface potential is suppressed by the gate voltage. As a result, the source-drain breakdown voltage of the MISFET of short channel length, which has a channel length of 1 .mu.m, a gate oxide thickness of 20 .mu.m and a source-drain junction depth of 0.35 .mu.m, is dropped to about 6 V, which is generally equal of an ordinary power supply voltage of 5 V. The transistor of short channel length described in the above is easily broken by the fluctuations in the power supply voltage. In the conventional MISFET of short channel length, in order to eliminate the above defect, there has been adopted the so-called "double diffused drain structure" in which are combined a highly concentrated diffusion layer having a shallow junction depth of about 0.2 .mu.m and a low concentrated diffusion layer having a larger junction depth of about 0.35 .mu.m. Thanks to the above structure, the BV.sub.DS value can be improved by about 1.5 to 2 V. As a result, the improved MISFET of short channel length according to the prior art can be usually obviated from being broken by the fluctuations in the power supply voltage. However, the above improved MISFET of small channel length has not been satisfied yet from the standpoint of reliability. In a long-term operation under a normal condition, more specifically, hot carriers are injected into a gate insulator by the high field crowding near the drain thereby to invite degradations such as fluctuations in the threshold voltage, increase in the surface state density, or reduction in the transconductance.
The description thus far made is directed to the MISFET element but can be substantially similarly applied to the structure of the CMOS which is constructed by combining two or more transistors. On the other hand, the CMOS has the following problems.
Here, the CMOS is a structure, in which a p-channel MOS (which will be referred to as a "PMOS") and an n-channel MOS (which will be referred to as a "NMOS") are coupled and formed on a common chip.
FIG. 1 is a sectional view showing the construction of the conventional CMOS having a gate length equal to or more than 2 .mu.m.
In FIG. 1, reference numeral 21 indicates an n-conductive type semiconductor substrate, and numeral 22 indicates a p-conductive type diffusion region which is formed in the semiconductor substrate 21 and which is called a "well". Numeral 23 indicates a field oxide, and numerals 24 and 25 indicate source and drain diffusion regions of the NMOS, which are formed in the well 22 and which are of n-conductive type having a maximum surface concentration equal to or more than 10.sup.20 cm.sup.-3. Numerals 26 and 27 indicate source and drain diffusion regions of the PMOS, which are of p-conductive type having a maximum surface concentration equal to or more than 10.sup.19 cm.sup.-3. Numerals 28 and 29 indicate a gate insulator and a gate electrode, respectively. Numerals 210 and 211 indicate a passivation film and a source or drain electrode, respectively.
The CMOSFET of the prior art construction having such a profiled drain structure has a variety of defects as the elements becomes minute: